The present invention relates to a MIS integrated semiconductor device in which two or more insulating gate (MIS) transistors having the same conductivity channels of different impurity density in the channel region are mounted on one chip.
More particularly, the present invention relates to the structure of a MIS integrated circuit in which a complementary MIS (CMIS) transistor and a MIS static induction transistor (SIT) are mounted on one chip.
Recently a demand for MIS integrated circuits, especially for MOS integrated circuits, has been increasing because of its simple design and stable manufacturing processes. Of these, a CMOS is chiefly used for watches, portable calculators, etc. because of its low power consumption at low-speed or direct-current operations. Although the CMOS is inferior to a bipolar transistor IC at a high-speed operation in the present state of development, improvements in high-speed operation and power consumption have been made by the recent advent of a punch-through MOS or a MOS-SIT. The advent of the IC with excellent performance both at a high speed and a low speed and with low power consumption is extremely advantageous in increasing the IC function and obtaining a circuit of optimum design.
The MOS-SIT is operable by shortening the gate length in comparison with the ordinary MOS transistor (MOST) to form a depletion layer between a source and a drain and forming an electric potential barrier in front of the source. If the MOST and MOS-SIT are formed by an identical design rule, however, it is simpler to lower the impurity density in the channel region at the SIT side. For that the MOS-SIT is formed on a high-resistant substrate and the MOST is formed inside a well, but the use of the high-resistant substrate often causes incomplete isolation between the elements, or a sufficient plane distance for isolation should be left. When the MOS-SIT is incorporated in a P-well in an n-type substrate, for example, it is generally more difficult to lower the density in the P-well than in the substrate and also latch-up easily occurs.